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Patent Searching and Data


Title:
PLL FREQUENCY SYNTHESIZER CIRCUIT
Document Type and Number:
Japanese Patent JPH03163912
Kind Code:
A
Abstract:

PURPOSE: To optimize the band characteristic (cut-off frequency) of an LPF corresponding to a system by using an SCF as the LPF to integrate a phase comparing output waveform and to generate the control voltage of a voltage controlled oscillator and further providing a means to vary the period of a clock signal to be applied to this SCF.

CONSTITUTION: A function block is equipped with an LPF 14 realized by the SCF and a programmable divider 13 for SCF to supply the clock signal to the LPF 14. A data set circuit 6 to set the frequency dividing ratio of the programmable divider 13 for SCF can be shared to set the frequency dividing ratio of a programmable divider 5 for frequency division to an output fIN of a VCO 1. In such a circuit, since the frequency dividing ratio of the programmable divider 13 for SCF can be freely set through the data set circuit 6 by external data 11, the clock signal to be applied to the LPF 14 by the SCF can be made variable.


Inventors:
KATO NAOYUKI
Application Number:
JP30425489A
Publication Date:
July 15, 1991
Filing Date:
November 21, 1989
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03L7/187; (IPC1-7): H03L7/187
Attorney, Agent or Firm:
Masuo Oiwa (2 outside)