To provide a PLL frequency synthesizer that increases a level of a phase detection output and decreases a temperature drift so as to enhance the accuracy and the stability.

Bipolar phase comparison outputs outputted from a phase comparator 1 of an ECL(emitter coupled logic) circuit configuration is supplied to a buffer circuit 2 of a CMOS logic circuit configuration, respectively, an adder 4 sums outputs of the buffer circuit 2, an output of the adder 4 is fed to a loop filter 5, where the output is converted into a DC voltage, an output of the loop filter 5 is fed to a voltage controlled oscillator 6 as a frequency control voltage, and the phase comparator compares a phase of the oscillation output of the voltage controlled oscillator 6 with a phase of an input signal. A voltage at which an intermediate voltage between a high level voltage and a low level voltage of a phase comparison output outputted from the phase comparator 1 is nearly equal to an input voltage given to the buffer circuit 2 is selected as a power supply voltage of the buffer circuit 2.