Title:
PLL ( PHASE LOCKED LOOP) CIRCUIT
Document Type and Number:
Japanese Patent JP3407197
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a PLL circuit that limits an operation of a frequency comparator circuit with its output in the case of a lock range of the phase comparator circuit and stably reads data by conducting phase lock even in the case of a recovered data pulse with much clock jitter.
SOLUTION: The PLL circuit A is provided with a frequency comparator circuit 1 that detects a phase difference based on a frequency difference between a recovered data pulse and an output frequency of a VCO 7, a phase comparator circuit 2 that detects a phase difference between the recovered data pulse with the VCO clock, a selection circuit 3 that selectively outputs an output of the frequency comparator circuit 1, a 2nd change pump circuit 5 that increases/ decreases an output voltage based on the output of the phase comparator circuit 2, a 1st change pump circuit 4 that increases/decreases an output voltage based on the output of the selection circuit 3, a loop filter 6 that eliminates an undesired component included in outputs of the 1st charge pump circuit 4 and the 2nd charge pump circuit 5, and the VCO 7 that oscillates a frequency corresponding to the output of the loop filter 6.
Inventors:
Mimi Miyata
Seiji Watanabe
Seiji Watanabe
Application Number:
JP33584199A
Publication Date:
May 19, 2003
Filing Date:
November 26, 1999
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G11B20/14; H03L7/08; H03L7/087; H03L7/093; H03L7/113; H04L7/033; H03L7/089; (IPC1-7): H03L7/113; H03L7/08; H03L7/087; H04L7/033
Domestic Patent References:
| JP3172024A | ||||
| JP237826A | ||||
| JP10112141A |
Attorney, Agent or Firm:
Kenichi Hayase