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Title:
PLL SYNTHESIZER CIRCUIT
Document Type and Number:
Japanese Patent JPH02177725
Kind Code:
A
Abstract:

PURPOSE: To reduce the lockup time at the change of the setting frequency without reducing the purity of an output signal by providing a changeover section short-circuiting a low pass filter only for a prescribed time at changeover of the setting frequency.

CONSTITUTION: In the even of a change of a setting signal fr outputted from a PLL arithmetic section 1 resulting from the revision of a setting frequency data DA< an analog switch 8 is closed based on an input of a strobe signal STB. Thus, an output signal SG1 of a charge pump 4 is outputted directly to a VCO 6 not through an LPF 5. Thus, an output signal SG 3 of the VCO 6 is shifted quickly up to a newly set frequency F2 from the original frequency F1 in a slight lockup time t2. Thus, after the strobe signal STB goes to an L level, an output signal SG 3 without any distortion based on the output signal SG 2 of the LPF 5 is outputted from the VCO 6.


Inventors:
NONAKA KAZUYUKI
AKIYAMA TAKEHIRO
TAKEGAWA KOUJI
Application Number:
JP33237188A
Publication Date:
July 10, 1990
Filing Date:
December 28, 1988
Export Citation:
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Assignee:
FUJITSU LTD
FUJITSU VLSI LTD
International Classes:
H03L7/187; H03L7/107; H03L7/183; H03L7/089; (IPC1-7): H03L7/187
Domestic Patent References:
JPS5533554B21980-09-01
Attorney, Agent or Firm:
Hironobu Onda (3 outside)



 
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