To provide a PLL synthesizer for adopting a fractional frequency division system employing a delta sigma circuit for realizing a low consumed current without deteriorating the characteristic.

A period shared by "H" levels is equal to a period shared by "L" levels in an output of a 1/2 fixed frequency divider 21 in the case of the 50% Duty cycle. An N counter 16 counts not only the number of rising edges but also the number of falling edges in the output of the 1/2 fixed frequency divider 21 without increasing the input frequency to the N counter 6. This can prevent the amount of Phase jump of a frequency division signal (Fdiv) 6 being the output signal of a variable frequency divider 2 from being increased, otherwise incurring deterioration in the noise characteristic of the PLL synthesizer, caused when an M value 14 being the frequency division ratio of the variable frequency divider 2 is switched. Thus, the PLL synthesizer is obtained, which has a characteristic unchanged from that of prior arts and attains the low current consumption by employing the 1/2 fixed frequency divider 21.