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Patent Searching and Data


Title:
PLL
Document Type and Number:
Japanese Patent JPS59115624
Kind Code:
A
Abstract:

PURPOSE: To attain the adjustment of free-run frequency and temperature compensation due to variance in manufacture of an integrated circuit by providing another control terminal at the outside of a PLL comprising a voltage controlled oscillator, a frequency divider, a phase comparator, a charge pump and an LPF.

CONSTITUTION: An output of the VCO2 is frequency-divided by the frequency divider 3 and the frequency dividing output and an external input signal 7 become inputs to the phase comparator 4. The charge pump 5 consists of a PCH MOS-TR31 and an NCH MOS-TR32, and when an external signal at a terminal 7 is faster than the signal frequency-dividing the oscillated frequency, the TR32 is turned on and when slower, the TR31 is turned on. In the figure, 6 is the LPF. In this case, the relation of fosc=f0×N is established, where fosc is the oscillated frequency, N is the frequency dividing ratio, and f0 is an external input frequency. Although it is necessary to stabilize the free-run frequency for the stable operation of the PLL, since a threshold voltage and an amplification factor or the like are changed depending on the manufacture conditions of the MOS-TRs and each parameter has each temperature characteristic, stable PLL conditions can not be maintained. In this invention, a gate of a PCH MOS-TR8 is controlled by resistors 11, 12 and a thermister 13 to stabilize the operation.


Inventors:
TSUJI MASUO
CHIHARA HIROYUKI
IKEJIRI HIROAKI
Application Number:
JP23234782A
Publication Date:
July 04, 1984
Filing Date:
December 22, 1982
Export Citation:
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Assignee:
SUWA SEIKOSHA KK
International Classes:
H03L7/099; H03L7/08; (IPC1-7): H03L7/08
Attorney, Agent or Firm:
Kisaburo Suzuki (1 outside)



 
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