Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
PLURAL PROCESSOR RESTARTING METHOD
Document Type and Number:
Japanese Patent JPH07154476
Kind Code:
A
Abstract:

PURPOSE: To prevent a signal link from being brought into a completely cutoff condition by restarting a slave processor divided into plural blocks with prescribed time difference.

CONSTITUTION: A system common managing processor 1 receiving restoration report processing 22 gives a notice that a signal network managing processor 2 is restored to signal processors #0-#n by performing restoration information processing 12. Each of the signal processors #0-#n performs processor number judging processing 30 which performs automatic restart when its own processor number shows an even number, and performs automatic restart processing 31 when its own processor number shows the even number, and performs the initialization of the signal link by performing automatic restart. When its own processor number shows an odd number in the processor number judging processing 30, the initialization of the signal link handled by an even-numbered processor is performed. and after that, timer setting processing 32 which takes sufficient time until the signal link can be used again is performed, and after that, the automatic restart is performed, then, the initialization of the signal link is performed.


Inventors:
ONO SHIGEO
Application Number:
JP32580493A
Publication Date:
June 16, 1995
Filing Date:
December 01, 1993
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
H04M3/22; H04M3/00; H04Q3/545; (IPC1-7): H04M3/22; H04M3/00; H04Q3/545
Domestic Patent References:
JPH05122746A1993-05-18
Attorney, Agent or Firm:
Masaki Yamakawa