Title:
PN PATTERN CHECK CIRCUIT
Document Type and Number:
Japanese Patent JPH04287530
Kind Code:
A
Abstract:
PURPOSE: To conduct the test with an optional frame spread arrangement pattern to a multi-frame with respect to the PN pattern check circuit used for a time division multiplex bus tester testing the data communication of a time division multiplex bus in the time division multiplex multi-frame communication system by means of loopback information of a PN pattern data.
CONSTITUTION: The circuit is provided with frame setting means 11-1n provided corresponding to each multi-frame and allocating a PN pattern data sent/ received in each frame and a parallel/serial conversion means 2 converting a frame setting parallel signal outputted from the frame setting means 11-1n into a serial signal.
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Inventors:
YOTSUMARU TAKEO
Application Number:
JP5251991A
Publication Date:
October 13, 1992
Filing Date:
March 18, 1991
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H04J13/00; (IPC1-7): H04J13/00
Attorney, Agent or Firm:
Sadaichi Igita