PURPOSE: To achieve a higher reliability of a pointer type electronic timepiece, by providing an initialization means which initializes a potential level of a driving signal formation circuit, prohibiting a first signal from being inputted into the driving signal formation circuit during a specified period based on a resistance and a time constant of a capacitor from the closing of a power source to prevent consumption of a battery otherwise closed by a continuous current to a motor generated at the closing of the power source.
CONSTITUTION: A differentiation circuit made up of a resistance 20 and a capacitor 21 and a NAND gate 22 are arranged. Consequently, a potential level at a CL of a flip flop can be fixed at a Hi level for a fixed time at the closing of a power source regardless of the level of a clock signal, Hi or Lo to be supplied from a frequency dividing circuit and the potential level of driving buffers 17 and 18 can be both a Hi level by writing a data signal into the flip flop for this period. Thus, it is possible to block the inflow of an undesired driving current to a step motor even after the elapse of the period determined by the resistance 20 and a time constant of the capacitor 21.
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JPS5324766A | 1978-03-07 | |||
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JPS4857678A | 1973-08-13 |