Title:
研磨予測評価装置、研磨予測評価方法、研磨予測評価プログラム、過研磨条件算出装置、過研磨条件算出方法及び過研磨条件算出プログラム
Document Type and Number:
Japanese Patent JP5515816
Kind Code:
B2
Abstract:
A polishing estimation/evaluation device includes a dividing unit, an overpolished area extracting unit, and a dummy modifying unit. The dividing unit divides a layout of an integrated circuit into a plurality of partial areas. The overpolished area extracting unit refers to an overpolishing condition indicating whether overpolishing occurs in a vicinity of a partial area based on a wiring density in the partial area and a wiring density in surrounding areas of the partial area, and extracts a partial area where the overpolishing occurs from the plurality of partial areas obtained by the division by the dividing unit. The dummy modifying unit modifies dummy wiring in the partial area where the overpolishing occurs extracted by the overpolished area extracting unit and/or dummy wiring in surrounding areas of the partial area to reduce the number of partial areas where the overpolishing occurs.
Inventors:
Daisuke Fukuda
Application Number:
JP2010026352A
Publication Date:
June 11, 2014
Filing Date:
February 09, 2010
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L21/304; B24B51/00; H01L21/02
Domestic Patent References:
| JP10293391A | ||||
| JP2010272611A | ||||
| JP2009182056A | ||||
| JP2006100571A | ||||
| JP2002319585A | ||||
| JP10144635A | ||||
| JP2002198419A | ||||
| JP2003347406A |
Attorney, Agent or Firm:
Hiroaki Sakai