Title:
多結晶シリコン薄膜トランジスタ及びその製造方法、表示装置
Document Type and Number:
Japanese Patent JP6976172
Kind Code:
B2
Abstract:
The present application discloses a method of fabricating a polycrystalline silicon thin film transistor, the method including forming an amorphous silicon layer on a base substrate having a pattern corresponding to a polycrystalline silicon active layer of the thin film transistor; the amorphous silicon layer having a first region corresponding to a source electrode and drain electrode contact region in the polycrystalline silicon active layer and a second region corresponding to a channel region in the polycrystalline silicon active layer; forming a first dopant layer on a side of the second region distal to the base substrate; forming a second dopant layer on a side of the first region distal to the base substrate; and crystallizing the amorphous silicon layer, the first dopant layer, and the second dopant layer to form the polycrystalline silicon active layer, the polycrystalline silicon active layer being doped with a dopant of the first dopant layer in the second region and doped with a dopant of the second dopant layer in the first region during the step of crystallizing the amorphous silicon layer.
Inventors:
Jien Min
Xiao Long Li
Tao Gao
Liangjien Li
Zenin Shu
Xiao Long Li
Tao Gao
Liangjien Li
Zenin Shu
Application Number:
JP2017545308A
Publication Date:
December 08, 2021
Filing Date:
July 25, 2016
Export Citation:
Assignee:
BOE TECHNOLOGY GROUP CO.,LTD.
International Classes:
H01L21/336; H01L29/786
Domestic Patent References:
| JP2003318120A | ||||
| JP2005079299A | ||||
| JP2008010860A | ||||
| JP2014060399A |
Foreign References:
| US20150294869 | ||||
| KR100646962B1 | ||||
| US20150147875 | ||||
| US20140077207 |
Attorney, Agent or Firm:
Yasuhiko Murayama
Shinya Mitsuhiro
Shinya Mitsuhiro