Title:
基板内のポア形成
Document Type and Number:
Japanese Patent JP7035171
Kind Code:
B2
Abstract:
Methods are provided for manufacturing well-controlled, solid-state nanopores and arrays thereof. In one aspect, methods for manufacturing nanopores and arrays thereof exploit a physical seam. One or more etch pits are formed in a topside of a substrate and one or more trenches, which align with the one or more etch pits, are formed in a backside of the substrate. An opening is formed between the one or more etch pits and the one or more trenches. A dielectric material is then formed over the substrate to fill the opening. Contacts are then disposed on the topside and the backside of the substrate and a voltage is applied from the topside to the backside, or vice versa, through the dielectric material to form a nanopore. In another aspect, the nanopore is formed at or near the center of the opening at a seam, which is formed in the dielectric material.
Inventors:
Klaus, Philip Allen
Johnson, Joseph Earl.
Johnson, Joseph Earl.
Application Number:
JP2020516720A
Publication Date:
March 14, 2022
Filing Date:
August 08, 2018
Export Citation:
Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
B81C1/00; B01J19/08; B81B1/00; B82Y5/00; B82Y40/00; C12M1/00; G01N27/00
Domestic Patent References:
| JP2015525114A | ||||
| JP2005125490A |
Foreign References:
| US20070020146 | ||||
| WO2016127007A2 | ||||
| WO2016187519A1 | ||||
| US20160313278 | ||||
| US20120108068 | ||||
| KR1020120000520A | ||||
| CN102901763A |
Attorney, Agent or Firm:
Sonoda/Kobayashi Patent Business Corporation
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