Title:
【発明の名称】スタティック型CMOS・フリップフロップ回路
Document Type and Number:
Japanese Patent JP3178610
Kind Code:
B2
Abstract:
PURPOSE:To stably operate the flip-flop circuit even at a low frequency by arranging two clocked inverter dynamic circuits in parallel and connecting an output terminal of a relevant inverter to cross-coupled inverters. CONSTITUTION:The flip-flop circuit consists of a master flip-flop circuit and a slave flip-flop circuit and a clocked inverter is adopted for a basic gate. An input output terminal of the clocked inverter 53 of the master flip-flop circuit is interconnected to an output input terminal of a clocked inverter 56 to form a flip-flop element and similarly an input output terminal of the clocked inverter 65 of the slave flip-flop circuit is interconnected to an output/input terminal of a clocked inverter 68 to form a flip-flop element. Thus, the signal latch function is realized without losing the high speed performance of the clocked inverter dynamic circuit.
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Inventors:
Yuuichi Kado
Masao Suzuki
Masao Suzuki
Application Number:
JP3899791A
Publication Date:
June 25, 2001
Filing Date:
February 12, 1991
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
H03K3/3562; H03K3/356; H03K5/151; (IPC1-7): H03K3/3562
Domestic Patent References:
| JP1248820A |
Attorney, Agent or Firm:
Takashi Sawai
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