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Patent Searching and Data


Title:
HIERARCHICAL MEMORY CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPH0635801
Kind Code:
A
Abstract:

PURPOSE: To increase the capacity of the buffer storages while suppressing the increase of the hardware quantity and also controlling these buffer storages in a store-in system in regard of a hierarchical memory control system which applies a hierarchical memory including a buffer storage of a CPU, the intermediate buffer storage of a storage controller, and a main storage.

CONSTITUTION: A buffer storage 2 uses the combination of an intra-page real address and the low order part of a logical address as a line address. At the same time, a tag means 7 of an intermediate buffer storage 5 controls the real address and the low order part of the logical address designated by a CPU 1. Meanwhile a storage controller 4 contains a mapping tag means 8 which controls the copy of the tag means of the storage 2 in addition to the means 7 of the storage 5. In such a constitution, the coincidence of data secured between both storages 2 and 5 is controlled.


Inventors:
AOKI NAOZUMI
TONE HIROSADA
MORIOKA TETSUYA
NISHIDA HIDEHIKO
Application Number:
JP18910692A
Publication Date:
February 10, 1994
Filing Date:
July 16, 1992
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F12/08; G06F15/16; (IPC1-7): G06F12/08; G06F15/16
Attorney, Agent or Firm:
Hiroshi Morita (1 person outside)