Title:
POWER AMPLIFICATION CIRCUIT
Document Type and Number:
Japanese Patent JPH01144812
Kind Code:
A
Abstract:
PURPOSE:To prevent excess through current directly flowing to a ground from a power amplification source without passing a load by delaying a time when a second transistor for driving can be operated from a time when a first transistor for driving can be operated with the aid of a delay circuit. CONSTITUTION:The delay circuit consisting of a capacitor 18 is added to the base circuit of a transistor 15 for switching. Therefore, the transistor 16 is kept being turn-on until the capacitor 18 is discharged after a function stopping signal 11 is changed from a high level to a low level. The transistor 15 is made to be turned off when the capacitor 18 is discharged soon after and the transistor 10 for driving is made to be a state that it can be operated. Then, at this time, the driving circuit of the transistor 9 for driving is sufficiently settled. Thus, the excess through current flowing to the ground from the power amplification source 8 can be prevented.
Inventors:
TAKI YOICHIRO
Application Number:
JP30512587A
Publication Date:
June 07, 1989
Filing Date:
December 01, 1987
Export Citation:
Assignee:
NEC CORP
International Classes:
H03F3/68; (IPC1-7): H03F3/68
Attorney, Agent or Firm:
Uchihara Shin
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