To provide a power amplifier capable of suppressing a leak current without increasing a chip area or cost.
Bias circuits B1 and B2 generate a bias voltage based on a reference voltage supplied from a reference voltage generating circuit VG and supply the bias voltage to amplifier transistors A1 and A2. An inverter INV boosts an enable voltage and outputs it. The reference voltage generating circuit VG is turned ON/OFF according to an output voltage of the inverter INV. The inverter INV has an enable terminal Ven, a power terminal Vcb, a transistor Tri1 and a FET resistance Fdi2. A base of the transistor Tri1 is connected to the enable terminal Ven, a collector is connected to the power terminal Vcb, and an emitter is grounded. The FET resistance Fdi2 is connected between the collector and the power terminal Vcb of the transistor Tri1. A gate electrode of the FET resistance Fdi2 is opened.
| JP3223066 | AMPLIFIER CIRCUIT |
| WO/2023/249896 | PROTECTION LOOP FOR POWER AMPLIFIER |
| WO/2022/217945 | DIGITAL POWER AMPLIFIER AND COMMUNICATION SYSTEM |
MIYASHITA MIYO
SUZUKI SATOSHI
MATSUZUKA TAKAYUKI
| JP2010124408A | 2010-06-03 | |||
| JP2006211023A | 2006-08-10 | |||
| JPH06350353A | 1994-12-22 | |||
| JPH0222855A | 1990-01-25 |
| WO2009081619A1 | 2009-07-02 |
Hideki Takahashi
Yoshimi Kuno