PURPOSE: To minimize the average power consumption by changing a clock speed so as to vary an action speed.

CONSTITUTION: The titled circuit is comprised of a variable speed clock generation part 1 to generate a variable speed clock signal 2, and a control part 3 composed of elements such as a CMOS to generate a clock speed control signal 4, which controls the variable speed clock generation part 1 in synchronization with the variable speed clock 2 according to a preset program, to said part 1. If a request to modify the clock speed is issued to the interior of the control part 3, it outputs the clock speed control signal 4 corresponding to the request to the variable speed clock generation part 1. It generates the variable speed clock signal 2 based on the control signal 4.