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Patent Searching and Data


Title:
POWER CONSUMPTION REDUCTION CIRCUIT
Document Type and Number:
Japanese Patent JP2003316486
Kind Code:
A
Abstract:

To prevent a through current due to signal fixation cancellation before supplying power, by stabilizing a signal state in reset cancellation when starting power supply in a power controllable circuit, in a power consumption reduction circuit of LSI having the power controllable circuit.

There are provided: a masking circuit 6 for fixing an input signal 4 to the power controllable circuit 1 and an input signal 3 from the circuit 1 to a regularly powered circuit 2 by a control signal 5 during power cutoff of the circuit 1; a delay circuit 7 for delaying the control signal 5; a reset masking circuit 10 for fixing a reset signal 9 to the circuit 1 by the output of the delay circuit 7 during the power cutoff of the circuit 1; and a control signal masking circuit 12 for fixing the control signal 5 by a state signal 11 representing a power supplying state of the circuit 1.


Inventors:
ADACHI YUSUKE
Application Number:
JP2002122585A
Publication Date:
November 07, 2003
Filing Date:
April 24, 2002
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F1/32; H03K19/00; (IPC1-7): G06F1/32; H03K19/00
Attorney, Agent or Firm:
Shohei Oguri (4 outside)