PURPOSE: To prevent the malfunction caused by an unstable clock for an integrated circuit which contains a phase control circuit where the oscillation of a master clock becomes unstable right after a power down state is canceled.

CONSTITUTION: A counting operation is carried out by a master clock 250 in each cycle of a frame signal 120 of fixed frequency supplied from the outside of an integrated circuit 100. Then the oscillation frequency of the clock 250 is measured based on the count value, i.e., in a fixed time. If the measured oscillation frequency is normal, a stable clock 250 is judged. If not, an unstable clock 250 is judged respectively. When the stable clock 250 is judged, the clock 250 is used as a system clock 750 of the circuit 100. Thus it is possible to prevent the malfunction of the circuit 100 that is caused by an unstable clock right after a power control state is canceled.