To suppress the occurrence of excessive surge voltage by performing PWM control where switching frequency does not fluctuate largely while a high-speed current control response is enabled.

A current deviation arithmetic circuit 15 gets a deviation between an output current on AC side of each phase of a power converter 11 and its current command, and a vector angle arithmetic circuit 19 calculates a current deviation vector angle, based on the deviation. A switching sequence logical circuit 21 generates a set of switching signals to be outputted next, based on the current deviation vector angle and the present switching state of the power converter 11, and the minimum pulse width setting circuit 22 outputs a minimum pulse width keeping time set value for keeping each state of the set of switching signals for a certain period.