To provide a power converter for compensating dead time and switching time variation in parallel operation by current-balancing three or more PWM(pulse width modulation) inverter units.

Outputs in the same phase (only U phase illustrated) of three inverter units 2A, 2B and 2C are combined by an interphase reactor 10U to obtain a U-phase output from the neutral point. For the leading edge and trailing edge of the PWM waveform from a PWM generating circuit 5, time-lag correction is made by a time-lag correcting circuit 2 of a current balance control circuit 11 or the like. For the correcting time, the mean value of output current of the respective units is obtained by an addition circuit and a divider, and the difference between the mean value and the output current of the respective units is obtained by a deviation detecting circuit. Proportional integral operation is conducted by a deviation control amplifier to obtain it as a time corresponding to the deviation by a limiting circuit according to plus or minus of the deviation.