PURPOSE: To shorten the detection cycle of the total power of a signal, by detecting total power at a cycle shorter than a frequency detecting cycle to enable the output of the detected result.
CONSTITUTION: An input signal INS is converted to a linear PCM code in an expander EXP and further subjected to series-parallel conversion. The signals of series bits B0WB7 in the time slot TS0 of INS are held to the expander EXP during the time slot TS0 of a signal PA and outputted to the multipliers M1, M2 of a debunching Fourier transform circuit DFT at every sub-time slots S0WS7. A timing signal t4 is inputted in the timings of the sub-time slots S6, S7 and a square indication signal SQR is made effective. Therefore, the values of B0W B7 are outputted while squared in the sub-time slots S6, S7. The value obtained by squaring the amplitude data of the input signal is outputted from EXP and, by integrating said valve for a difinite period, the total power of the input signal can be detected.
HATANO TAKASHI
TANAKA YASUO
SHIMOZONO RIYOUJI
SEKI YOUKO
