Title:
電力電子素子及びその製造方法並びに電力電子素子を含む集積回路モジュール
Document Type and Number:
Japanese Patent JP5692898
Kind Code:
B2
Abstract:
Power electronic devices including 2-dimensional electron gas (2DEG) channels and methods of manufacturing the same. A power electronic device includes lower and upper material layers for forming a 2DEG channel, and a gate contacting an upper surface of the upper material layer. A region below the gate of the 2DEG channel is an off region where the density of a 2DEG is reduced or zero. The entire upper material layer may be continuous and may have a uniform thickness. A region of the upper material layer under the gate contains an impurity for reducing or eliminating a lattice constant difference between the lower and upper material layers.
Inventors:
Gold
Summer
Kure
Choi
Yellow Hitoshi
Application light
Summer
Kure
Choi
Yellow Hitoshi
Application light
Application Number:
JP2010209412A
Publication Date:
April 01, 2015
Filing Date:
September 17, 2010
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H01L21/338; H01L29/778; H01L29/812
Domestic Patent References:
| JP2008244419A | ||||
| JP2000164604A | ||||
| JP2010010584A | ||||
| JP2009218566A | ||||
| JP4027706B2 | ||||
| JP2009507396A |
Foreign References:
| US20090200576 |
Attorney, Agent or Firm:
Shinya Mitsuhiro
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