Title:
POWER ESTIMATION FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2009042211
Kind Code:
A
Abstract:
To monitor the amount of power consumption with a simple means in applications, where the amount of power consumption in a semiconductor device is restricted.
The amount of power consumption in chips is estimated by measuring the juntion temperature of an integrated circuit. The temperature of a high-temperature section (a core section, or the like in a processor), and a low-temperature section (a part close to a heat sink, or the like) is measured by a plurality of sensor circuits incorporated in the integrated circuit to obtain a temperature difference. Arithmetic processing is performed from a thermal resistance value, or the like obtained in advance, thus estimating power consumption in chips.
Inventors:
WARREN PARKS
BOSTAK CHRIS
JAMES IGNOWSKI
BOSTAK CHRIS
JAMES IGNOWSKI
Application Number:
JP2008069177A
Publication Date:
February 26, 2009
Filing Date:
March 18, 2008
Export Citation:
Assignee:
INTEL CORP
International Classes:
G01R21/02; G01K13/00; G06F1/32; G06F15/78
Domestic Patent References:
| JP2005259753A | 2005-09-22 | |||
| JPH08213441A | 1996-08-20 | |||
| JPH01290249A | 1989-11-22 |
Attorney, Agent or Firm:
Akihiro Ryuka