Title:
POWER FACTOR CORRECTION CIRCUIT UTILIZING REVERSE SAWTOOTH WAVE
Document Type and Number:
Japanese Patent JP3398619
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a power factor correction circuit which has hardly the limitation of a duty factor with a high power factor by using a simple power factor correction circuit utilizing a reverse sawtooth wave.
SOLUTION: An output voltage Vmo of a multiplier 42 is a value obtained by multiplying an output voltage Ve of an error amplifying part and a reverse sawtooth wave signal Vsw by gain K as in an expression Vmo=K×Ve×Vsw. Then, the output voltage Vmo of the multiplier 42 is changed by the output voltage Ve of an error amplifier 21. An output voltage Vcs of a current detecting part 30 starts to increase at the point of time when a switching MOS transistor 12 is turned on, that is, when a reference clock signal of an oscillator 41 changes to a rise edge. The output voltage Vcs of the part 30 finally becomes the same as the output voltage Vmo of the multiplier 42 by such a manner that the output voltage Vcs of the part 30 increases. That is, the waveform of current iL caused to flow to an inductor coincides with the waveform of an input voltage, and consequently, a PFC circuit can offer a high power factor.
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Inventors:
Choi Rakchun
Application Number:
JP13491399A
Publication Date:
April 21, 2003
Filing Date:
May 14, 1999
Export Citation:
Assignee:
Fairchild Korea Semiconductor Co., Ltd.
International Classes:
H03K5/02; G05F1/70; H02M3/155; H02M7/12; H03K4/08; H03K5/00; H03K17/687; (IPC1-7): H03K17/687; H02M3/155; H02M7/12
Domestic Patent References:
| JP9140144A | ||||
| JP2000139079A |
Attorney, Agent or Firm:
Masatake Shiga (9 outside)