Title:
POWER FAILURE DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JP3225509
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To simply output a power failure detect signal which conforms to each rated input voltage of a plurality of different rated input voltages.
SOLUTION: A thyristor 19 is opened and closed according to the increase and decrease of an a.c. input voltage Vin. As a result, a resistor 18 is connected in series or separated to one voltage-dividing resistor 16. A voltage level of a medium point 17 between voltage-dividing resistors 15 and 16 input to one terminal of a comparator 25 is maintained within a predetermined range according to a change in the a.c. input voltage Vin whether or not the a.c. input voltage Vin is high or low. Therefore, a power failure detect signal conforming to every rated input voltage can be output even for a plurality of different rated input voltages. Since only the thyristor 19 and the resistor 18 are added to the circuit configuration, the circuit can be built simply.
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Inventors:
Saito Tsuguo
Kazuki Seino
Kazuki Seino
Application Number:
JP34176098A
Publication Date:
November 05, 2001
Filing Date:
December 01, 1998
Export Citation:
Assignee:
Aisin Co., Ltd.
International Classes:
H02J9/00; G01R19/165; H02J9/02; (IPC1-7): G01R19/165; H02J9/00; H02J9/02
Domestic Patent References:
| JP2290569A | ||||
| JP63179735U |
Attorney, Agent or Firm:
Mamoru Ushiki