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Title:
POWER-FAILURE DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JP2001264367
Kind Code:
A
Abstract:

To shorten the detection delay of the abnormal drop of a voltage and to suppress a wasterful power consumption in a power-failure detection circuit.

In the power-failure detection circuit which is connected to a power supply 11 used to output an AC voltage and which detects the abnormal drop of the AC voltage to be input from the power supply 11, a rectification means 12 which rectifies the AC voltage to be output from the power supply 11 is installed, a reference-level generation means 15 which generates a reference level is installed, a level comparison means 14 by which an input level corresponding to the voltage of a signal to be output from the rectification means 12 is compared with the reference level to be output from the reference-level generation means 15 so as to output a comparison result is installed, and a time identification means 17 is installed which identifies whether the length of the time in which the comparison result continues a specific state is large or small.


Inventors:
SHIMADA KATSURA
HATAMOTO YOSHIYUKI
Application Number:
JP2000076057A
Publication Date:
September 26, 2001
Filing Date:
March 17, 2000
Export Citation:
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Assignee:
FUJITSU DENSO
International Classes:
G01R19/165; H02J9/00; (IPC1-7): G01R19/165; H02J9/00
Attorney, Agent or Firm:
Furuya Fumio (1 person outside)