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Title:
POWER MOS-FET
Document Type and Number:
Japanese Patent JPS6263472
Kind Code:
A
Abstract:

PURPOSE: To reduce ON resistance, by forming a groove in the back surface of a semiconductor substrate layer beneath a gate so that the groove penetrates through the substrate layer and cuts into an epitaxial layer, and forming a high concentration layer having the same conductivity type as the substrate layer in the substrate layer facing a drain electrode.

CONSTITUTION: Anisotropic etching is performed in the back surface of a substrate layer 1 beneath each gate, and a groove 11 is formed. A high concentration N+ layer 12 is formed from the back surface side of the substrate layer 1, in which the groove 11 is formed. A drain electrode 10 is formed on the surface of the N+ layer 12. The groove 11 has the depth penetrating at least the substrate layer 1 and reaching an epitaxial layer 2. It is desirable that the depth of the groove is made as deep as possible in decreasing the ON resistance within a range the withstanding voltage can be maintained.


Inventors:
KUBO MASARU
OKADA KEIICHI
YOSHIOKA MINORU
ITO TAKUYA
YOSHIKAWA TOSHIBUMI
Application Number:
JP20390085A
Publication Date:
March 20, 1987
Filing Date:
September 13, 1985
Export Citation:
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Assignee:
SHARP KK
International Classes:
H01L29/78; H01L29/06; H01L29/08; H01L29/417; (IPC1-7): H01L29/52; H01L29/78
Attorney, Agent or Firm:
Kazuhide Okada



 
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