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Title:
POWER ON RESET CIRCUIT
Document Type and Number:
Japanese Patent JPH04192924
Kind Code:
A
Abstract:

PURPOSE: To attain power on reset without fail even when a power supply condition or the like is different by outputting a signal, which is reset by the output signal of a periodic time longer than the periodic time of the load signal of a counter, from its own counter.

CONSTITUTION: The period of a reset time is made longer than the periodic time of a counter load signal 2 so as not to reset the operation of a counter circuit 5 in the middle. When a counter signal 6 is changed from an H level to an L level and reset by a reset signal 3, a normal operation is started by finishing the reset of a power on reset requiring circuit 4 after the lapse of the reset time even when the initial state of the signal 6 is at the H level or the L level. In the normal operation state of the circuit 4, the circuit 5 is loaded periodically by the signal 2 and since the period of the signal 6 is longer than that of the signal 2, the circuit 5 is set at the L level at all times. Therefore, even when the power supply condition or the like is different, power on reset is attained without fail.


Inventors:
TANAKA HISAKO
KONOHI HAJIME
KIKUCHI KAZUYA
Application Number:
JP32775790A
Publication Date:
July 13, 1992
Filing Date:
November 27, 1990
Export Citation:
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Assignee:
NIPPON ELECTRIC ENG
International Classes:
G06M1/27; H03K17/22; H03K21/40; (IPC1-7): G06M1/27; H03K17/22; H03K21/40
Attorney, Agent or Firm:
Uchihara Shin



 
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