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Title:
POWER-ON RESETTING SYSTEM
Document Type and Number:
Japanese Patent JPH01284914
Kind Code:
A
Abstract:

PURPOSE: To prevent the cycle disturbance occurring among devices by continuing a reset state until a reference clock is stably supplied to release this reset state after the stable supply is secured with said reference clock and at the same time restarting the resetting action after a fixed time to initialize the phase of an internal clock of each device.

CONSTITUTION: A period of time during which a reference clock 2 received from an external oscillator 11 is stabilized is decided by an RC time constant circuit. Then a first reset signal 7 is transmitted to each device via an OR circuit 16 in a period A during which a signal 1 is stabilized by a waveform shaping circuit 14. When the clock 2 is stabilized, the clocks of the oscillator 11 are counted by a counter 13 via an FF 12. Then an ON signal B is transmitted via the OR secured between signals 4 and 5 when the count value of the counter 13 reaches a prescribed level. The counter 13 transmits again a resetting signal 4 after the output of the signal B and the count value of the counter 13 is equal to a fixed level. Then the counter 13 applies the second resetting action to each device via the OR secured between both signals 4 and 5.


Inventors:
KITAHARA TAKESHI
Application Number:
JP11551488A
Publication Date:
November 16, 1989
Filing Date:
May 12, 1988
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F1/24; G06F1/00; G06F1/04; (IPC1-7): G06F1/00; G06F1/04
Domestic Patent References:
JPH01236732A1989-09-21
JPS60131051U1985-09-02
Attorney, Agent or Firm:
Sadaichi Igita