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Title:
POWER-SAVING NOISE REDUCTION METHOD AND CIRCUIT
Document Type and Number:
Japanese Patent JP2008028202
Kind Code:
A
Abstract:

To provide a means capable of suppressing the enlargement of a device and the increase of power consumption, and efficiently reducing electromagnetic noise in relatively simple constitution.

A printed board (e) (insulation board) provided with a grounding conductor (f) on the back surface, has on its surface a signal line (a) of a pattern wiring for transmitting high speed signals to be the generation source of noise, a signal line (d) which is pattern wiring for transmitting relatively low speed signals near the signal line (a), and a signal line (b) arranged as pattern wiring roughly in parallel along the signal line (a) between the signal line (a) and the signal line (d). By transmitting the signals through the signal line (a) in an opposite direction to the signal line (b), the signal line (b) is made to generate an electromagnetic field for offsetting an electromagnetic field generated from the signal line (a), and the electromagnetic noise is reduced as radiated to the space from the signal line (a) of the generation source of the noise.


Inventors:
YOSHIDA KENICHI
Application Number:
JP2006199975A
Publication Date:
February 07, 2008
Filing Date:
July 21, 2006
Export Citation:
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Assignee:
NEC CORP
International Classes:
H05K1/02
Domestic Patent References:
JPS63100899U1988-06-30
Attorney, Agent or Firm:
Yasuo Suzuki
Yasunobu Usuda



 
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