To decrease an occupied area of a power generating circuit, and to reduce the number of external connecting terminals.

A clock generating circuit 1 is a buffer circuit consisting of a plurality of inverters, which is a circuit generating a clock CPCLK3 with an amplitude of VDD, and an inverted clock XCPCLK3 with the clock CPCLK3 inverted, based on an input clock CLK, and is used in common for the positive voltage power generating circuit 2 and the negative voltage power generating circuit 3. In the positive voltage power generating circuit 2, a flying capacitor C1 is connected between the external connecting terminals P1, P2, and the clock CPCLK3 is applied to one terminal of the flying capacitor C1 through the external connecting terminal P2. In the negative voltage power generating circuit 3, a flying capacitor C12 is connected between the external connecting terminals P2, P11, and the clock CPCLK3 is applied to one terminal of the flying capacitor C12 through the external connecting terminal P2.