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Patent Searching and Data


Title:
POWER SUPPLY CIRCUIT, DISPLAY AND ELECTRONIC EQUIPMENT
Document Type and Number:
Japanese Patent JP2002291231
Kind Code:
A
Abstract:

To stand a large current when a load is particularly large and reduce the loss in power consumption when the load is normally small in a charge pump and booster circuit using capacitors alternately charged and discharged.

A pre-booster circuit 4 and a post-booster circuit 6 sequentially boost a power supply voltage VCC and output voltages VEM, VOUT. An output voltage monitor circuit 8 monitors the voltage VEM. If the voltage VEM decreases, an instructing signal (up) for enhancing a boosting capability is outputted. If the voltage VEM unnecessarily increases, an instructing signal (down) for reducing the boosting capability is outputted. A boosting clock forming circuit 2 sets frequencies of boosting clock signals A, B in response to the instructing signals. Since the booster circuits 4, 6 operate with capabilities corresponding to the loads, the loss in power consumption is reduced when the load is normally small.


Inventors:
YAMAZAKI TAKU
Application Number:
JP2001093913A
Publication Date:
October 04, 2002
Filing Date:
March 28, 2001
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
G02F1/13; G02F1/133; G09G3/20; G09G3/36; H02M3/07; (IPC1-7): H02M3/07; G02F1/13; G02F1/133; G09G3/20; G09G3/36
Attorney, Agent or Firm:
Masanori Ueyanagi (1 outside)