PURPOSE: To omit a latch circuit and a counter for simplification of a circuit by setting a main processor in a power saving mode to save the power supplied from a power supply control circuit and breaking the power supply when necessary.
CONSTITUTION: When the conditions are satisfied to set a main processor 1 in a power saving mode, the processor 1 delivers the signals to terminals R0WR7 of a secondary processor 2 from terminals D0WD7 to inform that said conditions are satisfied. At the same time, the processor 1 informs its output to the processor 2 by a command signal. The processor 2 receives the output and latches it at an input/output port. Then a power saving indication signal is delivered to a terminal PS of the processor 1 from a terminal R10 to set a power saving mode. The time counting is started for cut-off of the power supply, and the propriety for cut-off of the power supply is inquired to the processor 1 when the prescribed time counting is over. When the cut-off of the power supply is permitted by an answer signal, a prescribed signal is sent to a power supply control circuit 3 to cut off the power supply.
NISHIDA YUKITERU
NOHAMA MAMORU
| JP57189031B | ||||
| JPS58106622A | 1983-06-25 | |||
| JPS56110119A | 1981-09-01 | |||
| JPS5752931A | 1982-03-29 | |||
| JPS5850060A | 1983-03-24 |