Title:
POWER SUPPLY REINFORCEMENT METHOD AND SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH04318396
Kind Code:
A
Abstract:
PURPOSE: To provide a technology which can effectively suppress power supply noise with a simple method.
CONSTITUTION: Diodes D1 and D2 are placed in a bridge form between a low potential side power supply Vss1 line and a low potential side power supply Vss2 line and a diode D3 is placed in a bridge form between the low potential side power supply Vss2 line and a low potential side power supply Vss3 line. Thus, a potential rise on the low potential side power supply Vss1 line and a potential rise on the low potential side power supply Vss2 line are suppressed and power supply noise is reduced.
Inventors:
HATANO SUSUMU
NISHIMOTO KENJI
KITANO JUN
NISHIMOTO KENJI
KITANO JUN
Application Number:
JP11115291A
Publication Date:
November 09, 1992
Filing Date:
April 16, 1991
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G11C11/413; G11C11/401; G11C11/407; H01L21/822; H01L27/04; (IPC1-7): G11C11/413; H01L27/04
Attorney, Agent or Firm:
Shizuyo Tamamura