Title:
POWER UP DETECTING CIRCUIT OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3945791
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent a malfunction, by enabling the internal circuit to be in a deactivated state when the detection signal of a first voltage level is applied and outputting the waveform, which is the same as the waveform of an input, when a second voltage level is applied.
SOLUTION: An NMOS transistor 240, to which an output signal VCCH of the waveform of an input voltage VINT is fed back, is activated and a node N2 of the input stage of an output buffer 220 is maintained in a logic L level. Thus, the output buffer 220 and the transistor 240 are latched so that the signal VCCH is continuously outputted with the waveform which is same as the waveform of the voltage VINT. Since the signal VCCH follows the changes of the waveform of the voltage VINT, the signal VCCH is activated only when the voltage VINT becomes an off state. Thus, even though the voltage VINT is reduced to a low voltage level during a self-refreshing operation, the malfunction, in which a master clock is deactivated and passes through the self-refreshing operation, is prevented.
Inventors:
Yu Yanagi
Application Number:
JP2467098A
Publication Date:
July 18, 2007
Filing Date:
February 05, 1998
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C11/401; G11C11/4072; G05F1/56; G05F3/26; G11C5/14; G11C11/4074; G11C11/419; H03K17/22; (IPC1-7): G11C11/401; G05F1/56; G11C11/407
Domestic Patent References:
| JP4074015A | ||||
| JP6296126A | ||||
| JP63246919A | ||||
| JP7169270A | ||||
| JP6196989A | ||||
| JP55018381A |
Attorney, Agent or Firm:
Makoto Hagiwara
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