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Patent Searching and Data


Title:
POWER UP DEVICE IN SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0737384
Kind Code:
A
Abstract:

PURPOSE: To detect a power source from the slow ramp like leading to the high speed leading without consuming a standby current like DC.

CONSTITUTION: At the time of a ramp like leading, a transistor MNH is put ON in a low voltage, and a N21 is made to be a high level initial state while a N22 is made to be low level initial state by the help of a transistor MP. During a slow leading, the capability increasing the N21 by the transistor MP is larger than the capability increasing the node N22 by a transistor MPH. Since the MNH is provided with a low threshold voltage, the decreasing process in the node N22 is speeded up. A capacitor CG prevents the node N22 from being charged at a high speed with the transistor MPH. When the node 21 is started in a high voltage level state, the internal voltage connected to the gate of a transistor MNI is risen, and when the MNI is turned ON, the node N21 is begun to decrease and the state of the node N22 and a PUD is inverted.


Inventors:
SHII WAI TSUAI
DEII JIEI RETSUDOWAIN
Application Number:
JP19158191A
Publication Date:
February 07, 1995
Filing Date:
July 31, 1991
Export Citation:
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Assignee:
TEXAS INSTRUMENTS INC
International Classes:
G11C11/407; G11C11/401; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): G11C11/407; G11C11/401; H01L21/8242; H01L27/108
Attorney, Agent or Firm:
Akira Asamura (3 outside)