PURPOSE: To attain a high speed reading operation following a writing operation by starting pre-charging with a pulse produced from a write enable signal before pre-charging with a pulse produced from an address fluctuation detector.
CONSTITUTION: When a writing operation is changed to a reading operation, N channel MOS transistors 16 and 17 are turned ON by a pulse WE produced by a write enable signal and a bit line BL and the inverse BL are charged to specified levels. Then, the bit line BL and the inverse BL are completely pre-charged in transistors 11 to 13 which respond to a pulse inversion EQ produced from an address fluctuation detector (ATD). Transistors 14 and 15 are always turned ON by high resistance and a current for compensating for the leaked amount from the bit line during a long cycle is supplied. Thus, by performing pre-charging in two stages, a high speed for a reading operation following a writing operation is attained.
TE SUN JIYUN
SAN KI WAN
| JPS61190787A | 1986-08-25 |