To provide a pre-scaler circuit capable of obtaining a clock signal of a desirable frequency by small circuits with respect to an input of the clock signal of a different frequency.
In a pre-scaler device, a plurality of clock signals of a different frequency are input as a first basic clock signal, and the basic clock signal is divided to generate the clock signal of a desirable frequency. The pre-sealer device has a plurality of first pre-scalers 2, 3 and a single second pre-scaler 4. In the plurality of first pre-scalers 2, 3, when a common divisor of a frequency of a plurality of the first basic clock signals is an intermediate frequency, each of the plurality of basic clock signals of the different frequency is input, and each of the second basic clock signals of the intermediate frequency is generated. In the single second pre-scaler 4, the second basic clock signal output from the plurality of first pre-scalers is input and divided to generate the clock signal of the desirable frequency.
JP7393079 | semiconductor equipment |
JPH0468911 | SEMICONDUCTOR INTEGRATED CIRCUIT |
JP2000138568 | CLOCK SIGNAL SWITCHING DEVICE |
KAJIWARA SHINSUKE
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