PURPOSE: To preclude the possibility of destruction of a succeeding transformer or speaker by making a value holding by a pre-value holding section forcibly zero when an error is consecutive and a duration time of a pre-value hold exceeds a specified time.

CONSTITUTION: D flip-flops 23 of a bit number of a parallel voice data are provided to a pre-value hold section 4 and a voice data is fed to a data input terminal D of a said flip-flop 23 for each bit. An error signal and a clock are fed to an AND circuit 24, and a clock is extracted only when an error signal is at a high level (indicating no error) and the clock is fed to a clock input terminal CLK of the flip-flop 23, which fetches the voice data and latched. When the error signal is at a low level, the flip-flop 23 stops fetching the incoming voice data. Thus, flowing of an overcurrent to a transformer or a speaker is prevented.