Title:
ニューラルネットワークプロセッサで使用される重みのプリフェッチ
Document Type and Number:
Japanese Patent JP7071577
Kind Code:
B2
Abstract:
A circuit for performing neural network computations for a neural network, the circuit comprising: a systolic array comprising a plurality of cells; a weight fetcher unit configured to, for each of the plurality of neural network layers: send, for the neural network layer, a plurality of weight inputs to cells along a first dimension of the systolic array; and a plurality of weight sequencer units, each weight sequencer unit coupled to a distinct cell along the first dimension of the systolic array, the plurality of weight sequencer units configured to, for each of the plurality of neural network layers: shift, for the neural network layer, the plurality of weight inputs to cells along the second dimension of the systolic array over a plurality of clock cycles and where each cell is configured to compute a product of an activation input and a respective weight input using multiplication circuitry.
Inventors:
Ross, Jonathan
Application Number:
JP2021159352A
Publication Date:
May 19, 2022
Filing Date:
September 29, 2021
Export Citation:
Assignee:
Google LLC
International Classes:
G06F15/80; G06F17/10; G06N3/063
Domestic Patent References:
| JP3131965A | ||||
| JP5346914A | ||||
| JP6131308A |
Attorney, Agent or Firm:
Fukami patent office