Title:
PREFIXING SYSTEM
Document Type and Number:
Japanese Patent JPS59121455
Kind Code:
A
Abstract:
PURPOSE:To set continuously an address which can be used by each processor regardless of the number of processor by deciding the upper bit which is replaced in response to the size of a fixed region after providing a register which sets the data showing the start address of the fixed region to the processor. CONSTITUTION:The address data 11 of a prescribed bit is produced by a processor, and the fixed region of the upper bit of the data 11 is set to a register 12. The data 11 is different in response to each processor, and the data of the upper bit is applied to a zero detecting circuit 13 to check whether all data are zero. A multiplexer 14 selects the data of the registter 12 with the zero detecting signal, and the new address data is delivered. At the same time, the maximum applicable address is set to a register 15. Then the data of said maximum address is compared with the upper bit by an arithmetic circuit 16 in order to prevent the input of address data to the fixed region. Thus address data applicable to each processor are continuously set.
Inventors:
MAEDA AKIRA
Application Number:
JP22770482A
Publication Date:
July 13, 1984
Filing Date:
December 28, 1982
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
G06F12/00; G06F12/02; G06F13/00; G06F15/16; G06F15/177; (IPC1-7): G06F15/16
Attorney, Agent or Firm:
Takehiko Suzue