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Title:
PREPARATION OF FIELD-EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPH04277632
Kind Code:
A
Abstract:

PURPOSE: To simplify the manufacturing steps of field-effect transistors, and to maintain the uniform characteristics by ensuring the alignment in a field.

CONSTITUTION: A pair of source electrodes 3 and 3' and a pair of drain electrodes 4 and 4' are formed over a semi-insulated GaAs substrate 1 which includes active regions 2. The substrate is then coated with a photoresist 5 by spincoating. Two areas designated for gate electrodes on the substrate are then exposed to light using photomasks, which are different from each other in transmissivity, on the areas, respectively. The photoresist 5 is then developed to a predetermined extent. The gate electrode area of an enhancement mode FET on the semi-insulating GaAs substrate 1 is subjected to the recess etching. Finally, Ti, Pt and then Au are sequentially vapor-deposited over the substrate with the photoresist 5 being covered with a mask, thereby constituting a gate electrode 7'. The unnecessary Ti, Pt and Au are then lifted off from the photoresist 5.


Inventors:
ISHIHARA DAIZO
Application Number:
JP6537891A
Publication Date:
October 02, 1992
Filing Date:
March 05, 1991
Export Citation:
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Assignee:
MURATA MANUFACTURING CO
International Classes:
H01L29/417; H01L21/338; H01L29/812; (IPC1-7): H01L21/338; H01L29/50; H01L29/812