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Title:
プリプレグ、金属張積層板、プリント配線基板および半導体パッケージ
Document Type and Number:
Japanese Patent JP6972522
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a prepreg capable of reducing warpage of a semiconductor package.SOLUTION: The prepreg of the present invention includes a first resin layer, a fiber substrate layer comprising a fiber substrate impregnated with a thermosetting resin composition containing silica, and a second resin layer, stacked in this order. The fiber substrate is constituted by weaving a warp strand comprising aggregation of a plurality of warps and a weft strand comprising aggregation of a plurality of wefts, to intersect each other. In a cross section parallel to the stacking direction of the prepreg and perpendicular to the extension direction of the warp strand, the silica is present among warps in the warp strand.SELECTED DRAWING: Figure 1

Inventors:
Kenta Sato
Application Number:
JP2016171115A
Publication Date:
November 24, 2021
Filing Date:
September 01, 2016
Export Citation:
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Assignee:
Sumitomo Bakelite Co., Ltd.
International Classes:
C08J5/24; B29B11/16; B32B5/00; B32B15/08; B32B17/04; C08K3/36; H05K1/03
Domestic Patent References:
JP2011178992A
JP2012167256A
Attorney, Agent or Firm:
Shinji Hayami