To provide a prescaler with broadband.
The prescaler 33 is provided with a buffer section 41 and a counter 43. The buffer section 41 includes: a first stage circuit 52 comprising a plurality of inverter circuits 52a to 52c different in drive capability; a plurality of inverter circuits 54a to 54d connected in series; and a feedback circuit 55. Any of the inverter circuits 52a to 52c of the first stage circuit 52 receives a signal fv by any combination of first switch sections 51 and second switch sections 53, output terminals of the inverter circuits 52a to 52c are connected to a post-stage inverter circuit 54a, and the drive capability of the first stage circuit 52 is varied. The feedback circuit 55 acts like a resistor set by voltages V1, V2.
COPYRIGHT: (C)2008,JPO&INPIT
AOKI KOUKI
BABA HIROSHI
| JP2003022537A | 2003-01-24 | |||
| JP2004134828A | 2004-04-30 | |||
| JPH04172716A | 1992-06-19 |
Makoto Onda