To provide a prescaler circuit which has enlarged margin of delay time at which a malfunction occurs, when switching the frequency dividing number.

The circuit is provided with a frequency dividing switching part 59a, comprising first to sixth D-type flip-flop circuits 54a, 54b, 54c, 54d, 54e, and 54f, first and second AND circuits 55a and 55b, and first and second OR circuits 56a and 56b; and a number change portion of discriminating circuits 59a configured by 56b, a dividing switch control unit 59b comprising a third AND circuit 55c, a third OR circuit 56c, and first and second NOR circuits 57a and 57b. The frequency dividing switching part has the function of controlling the frequency dividing numbers N, N+1, N+2 via the first and second AND circuits 55a and 55b by control of a modulus signal to be inputted to the first and second NOR circuits. The dividing switch control unit has the function of controlling 8 and 16 frequency dividing by control of the modulus signal to be inputted to the third AND circuit.