Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3159154
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the number of wiring layers by eliminating the need for increasing the element area of a resistance circuit by increasing the contact resistances of polysilicon plugs, which connect a diffusion layer with a wiring layer by diffusing the phosphorous in the plugs in the wiring layer through heat treatment.
SOLUTION: Silicon plugs 109 are formed by embedding phosphorus-doped silicon in contact holes 108 and etching back the silicon. It is also possible to inject phosphorous into non-doped silicon after the silicon is buried in the contact holes 108 at the time of forming the plugs 109. Then a wiring layer 110 is formed on an interlayer insulating film 107, and the phosphorous contained in the polysilicon plugs 109 formed in a resistance circuit area is diffused in the wiring layer 110 through heat treatment. Consequently, the contact resistances of the plugs 9 are increased. Therefore, a resistance circuit having a large resistance value can be formed, because the resistance values of the plugs 109 can be increased, when the plugs 109 are formed in this way.
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Inventors:
Yuichi Takada
Application Number:
JP4047398A
Publication Date:
April 23, 2001
Filing Date:
February 23, 1998
Export Citation:
Assignee:
NEC
International Classes:
H01L21/28; H01L21/3205; H01L21/768; H01L21/822; H01L23/52; H01L27/04; (IPC1-7): H01L21/28; H01L27/04
Domestic Patent References:
| JP9219493A | ||||
| JP7122713A |
Attorney, Agent or Firm:
Yasuyuki Hata