Title:
PRESHIFT CIRCUIT
Document Type and Number:
Japanese Patent JPS6247870
Kind Code:
A
Abstract:
PURPOSE:To obtain a delay time in response to the change of a preshift pattern and its length by using an external control signal to secure an optional control for the selection of bits of a preshift bit signal. CONSTITUTION:A shift register circuit 3 converts a serial code signal (a) into a parallel code signal (g) and delivers it. While a pattern controller 1 supplies a pattern control signal (c) sent from an external circuit and delivers a pattern signal (f) and a store signal (e). A bit selector circuit 4 supplies the signals (f) and (e) and delivers a bit selector signal (h). Then pattern register circuits 5 and 6 deliver the stored pattern signals 1i and 2i. A bit selector circuit 7 supplies the signals (g) and (h) and delivers a no-delayed signal (j) to a lower order circuit. A pattern comparators 8 and 9 and a rest pattern circuit 10 delivers preshift bits 1k-3k respectively. The delay circuits 11-13 give delays to the signals 1k-3k and an OR circuit 14 secures the OR of those signals 1k-3k.
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Inventors:
TAKIGAMI HIROBUMI
Application Number:
JP18891085A
Publication Date:
March 02, 1987
Filing Date:
August 28, 1985
Export Citation:
Assignee:
NEC CORP
International Classes:
G11B5/09; G11B20/10; (IPC1-7): G11B20/10
Attorney, Agent or Firm:
Naotaka Ide