PURPOSE: To prevent an up/down counter from malfunctioning even if an asynchronous clock signal or up/down control signal is inputted by counting the outputs of two flip-flop circuits which delay the output of a 1st flip-flop circuit by a constant time and controlling the counting direction of the up/down counter.

CONSTITUTION: The up/down counter inputs a clock signal to be counted by the 1st flip-flop circuit 4 to normalize the clock signal and also inputs the up/ down control signal for controlling the up/down mode of the up/down counter 7 by a 3rd flip-flop 6 to match the up/down control signal with the normalized clock signal. Then the normalized clock signal is delayed by the 2nd flip-flop circuit 5, the output of the 3rd flip-flop circuit 6 is used as the up/down control signal of the up/down counter 7, and the output of the 2nd flip-flop 5 is used as the clock signal of the up/down counter 7. Consequently, the up/down counter is prevented from malfunctioning.