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Title:
PREVENTION SYSTEM AGAINST MALFUNCTION OF DETECTING CIRCUIT FOR PROCESSOR MALFUNCTION
Document Type and Number:
Japanese Patent JPS6029849
Kind Code:
A
Abstract:

PURPOSE: To prevent malfunction even in case of wrong access to an undefined address and to continue normal data processing by stopping the output operation of an abnormality detecting circuit when the monitor function of a processor is operated externally.

CONSTITUTION: While a data processor is in operation, "0" is set in a register 5 and an AND circuit 4 is on; when a processor 2 accesses an undefined address, abnormality is detected 3 and the AND circuit 4 outputs abnormality to stop the processor 2. Now, when a monitor command is inputted on a keyboard 1 so as to monitor the operation state of the processor through external operation, the processor 2 sends 1 to the register 5 to turn off the AND circuit 4. Even if access to the undefined address is attained by mistake in said state and abnormality is detected 3, the abnormality signal is cut off by the AND circuit 4. When a monitor program ends, the register 5 is reset. Consequently, malfunction in monitoring operation is prevented.


Inventors:
MORIYAMA YUTAKA
OOE SHIGERU
Application Number:
JP12736383A
Publication Date:
February 15, 1985
Filing Date:
July 13, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/00; G06F11/07; (IPC1-7): G06F11/00
Domestic Patent References:
JPS5086952A1975-07-12
JPS55159256A1980-12-11
Attorney, Agent or Firm:
Akira Yamatani